RISC / CISC
Q.1 Define RISC / CISC?
Ans. RISC: stands for Reduced Instruction Set Computing. It is strategy of computer design that simplified instructions can provide higher performance but condition is that the simplicity enables much faster execution of each instruction.
CISC: It stands for Complex Instruction Set Computing. It is a computer in which single instructions can executes various low level operations. And also able to executes multistep operations. Q.2 Compare the architecture of RISC / CISC ?
Ans. CISC RISC
- More Emphasis on hardware More Emphasis on software
- Multiclock, complex instruction Single clock, only reduced instruction
- Memory to memory: “Load” and “Store” Register to register: “Load” & “store”
incorporated in instruction independent of instruction
4. Small code size Large code size
5. High cycles per sec. low cycles per sec.
6. For storing complex instruction More transistors transistors are used
Q.3 Explain the focus area of CPU design of CISC / RISC?
Ans.
- Data path like ALU & pipelines
- Control unit that control the data path.
- Memory components like registers & caches.
- Pad transceiver circuitry.
- Clock circuitry.
- Implementation of logic gates.
Q.4 Explain the types of devices used to implement logic?
Ans.
- Small scale Integration Transistor transistor logic chips.
- Programmable logic device & Programmable array logic.
- CMOS arrays.
- CMOS ASICs.
- Emitter coupled logic gates array.
- Field Programmable Gate Array.
Q.5 Explain major task of CPU design Project?
Ans.
- Programmable visible instruction set architecture.
- High level synthesis & RTL implementation.
- RTL verification.
- Circuit design for speed critical component.
- Logic synthesis.
- Timing analysis
- Floor planning, place and route of logic gates.
- Checks for single integrity & chip manufacturability.
Q.6 Explain the advantages of RISC?
Ans.
- Speed: Simplified Instruction Set allows pipelines, superscalar design RISC processor to achieve 2 to 4 times performance of CISC processor.
- Simpler Hardware: It uses much less chip space such that extra function like mamory management unit can also be placed in same units.
- Shorter Design Cycle: Its advantage is that technological deployment is soonar than corresponding CISC.
Q.7 Explain Pipelining?
Ans. It is also known as Assembly line. It is a technique to process on multiple instruction on the same time. It allows the the instruction to be executed efficiently.
Stages of Pipelining
- Fetch instruction from memory.
- Decode the instruction.
- Execute the address and calculate address.
- Excess the operand in data memory.
- Write the result into register.
Q.8 Explain the feature of CISC?
Ans.
- Instruction can operate directly on memory.
- Smaller no of general purpose register.
- Instruction takes multiple clock to execute.
- Less no. of lines of code.
Q.9 Explain Semantic gap of RISC & CISC?
Ans. For improving efficiency of software development various powerful programming lang. like C, C++, JAVA etc have come up. They provide abstraction, conciseness and power. By this evolution semantic gap grows. To enable efficient compilation of high level programs CISC & RISC are 2 option. CISC involve very complex architectures including large no. of instruction & addressing modes. While RISC design involves simplified instruction set & adapt it to the real requirement of user programs.
Q.10 Explain the advanced RISC Machine (ARM)?
Ans.
- ARM architecture used most widely 32 bit ISA in term of number product.
- They are originally conceived as a processor of desktop of PC by Acron Computers, now market dominated by x86 family used by IBM PC compatible computers.
- Suitable for low power application.
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