Digital electronics – JK Flip-Flop

Apr 29 • General • 7641 Views • 2 Comments on Digital electronics – JK Flip-Flop

DIGITAL ELECTRONICS-JK FLIP FLOP

Flip-flops are the building blocks of any sequential logic circuits. A flip-flop is a device very like a latch in that it is a bi stable multivariate, having two states and a feedback path that allows it to store a bit of information. The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs can change as soon as the inputs do (or at least after a small propagation delay). A flip-flop, on the other hand, is edge-triggered and only changes state when a control signal goes from high to low or low to high. This distinction is relatively recent and is not formal, with many authorities still referring to flip-flops as latches and vice versa, but it is a helpful distinction to make for the sake of clarity.

There are several different types of flip-flop each with its own uses and peculiarities. The four main types of flip-flop are : SR, JK, D, and T.

JK FLIP FLOP

JK means Jack Kilby, a Texas instrument engineer who invented IC. The two inputs of JK Flip-flop is J (set) and K (reset). A JK flip-flop is nothing but a RS flip-flop along with two AND gates which are augmented to it.Here J and K are synchronous inputs .The valid condition of SR Flip-flop is overcomed with the help of extra feedback to 1st stage.

100px-JK_Flip-flop_(Simple)_Symbol.svg

                                                                        Block Diagram

Truth table

The characteristic table explains the various inputs and the states of JK flip-flop.

JKQnextComment
00QprevHold state
010Reset
101Set
11QprevToggle

When J=K=0

When both J and K are 0, the clock pulse has no effect on the output and the output of flip-flop is same as its previous value. This is because when both the J and K are 0, the output of their respective AND gate becomes 0.

When J=0, K=1

When J=0, the output of the AND gate corresponding to J becomes 0(i.e.) S=0 and R=1. Therefore Q’ becomes 0. This condition will reset the flip-flop. This represents the RESET state of Flip-flop.

When J=1, K=0

In this case, the AND gate corresponding to K becomes 0(i.e.) S=1 and R=0. Therefore Q becomes 0. This condition will set the Flip-flop. This represents the SET state of Flip-flop.

When J=K=1

Consider the condition when CP=1 and J=K=1. This condition will cause the output to complement again and again. This complement operation continues until the Clock pulse goes back to 0. Since this condition is undesirable, we have to find a way to eliminate this condition. This undesirable behaviour can be eliminated by Edge triggering of JK flip-flop or by using master slave JK Flip-flops.

Excitation Table

QQnextJKComment
000XHold state
011XSet
10X1Reset
11X0Hold state

mainjk

Characteristic equation 

Qnext    =Qprev‘J +Qprev K’

 A circuit symbol for a positive-edge-triggered JK flip-flop

516px-JK_timing_diagram.svg
JK flip-flop timing diagram

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a “flip” or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.

Applications Of JK Flip-Flops

Counters,Frequency Divider,Shift Registers,Storage Registers.These are the various types of Flip-flops which are being used in Digital electronic circuits and the applications of Flip-flops are as specified above.

QUESTIONS AND ANSWERS

Q .J-K flip-flop is in a “no change” condition when ________.

a)J= 1 and k=1

b)J= 1and k=0

c)J= 0and k=1

d)J=0 and k=0

Ans :option d

Q.A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

a)clock is low

b)slave is transferring

c)flip flop is reset

d)clock is high

Ans:option d 

 

Q:What is “race  around condition” in JK Flip flop?

Ans:When clock pulse is high and both J and K are high. This condition cause the output to complement again and again. This complement operation continues until the Clock pulse goes back to 0.  This condition is called “race around condition “.

This undesirable behaviour can be eliminated by Edge triggering of JK flip-flop or by using master slave JK Flip-flops.

 Q:What are the applications of JK F/F?

Ans: The application are as follows:

a)Counters

b)Frequency Dividers

c)Shift Registers

d)Storage Registers

Q.In JK Flip-flop what is this JK?

Ans:JK means Jack Kilby, a Texas instrument engineer who invented IC. The two inputs of JK Flip-flop is J (set) and K (reset).

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