# Introduction to Flip Flops and Latches

Oct 29 • Notes • 13452 Views • 2 Comments on Introduction to Flip Flops and Latches

Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit .There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major differences in the flip flop. How can we make a circuit out of gates that is not.  The answer is feed-back, which means that we create loops in the circuit diagrams so that output values depend, indirectly, on themselves. If such feed-back is positive then the circuit tends to have stable states, and if it is negative the circuit will tend to oscillate. Here in this post you will find out Introduction to Flip Flops and Latches which are the most commonly used bistable devices but they are differ in the method of changing their state, used in digital electronics in order to better understand the topic.

Their are two types of triggering/activation in the memory element devices.

• Pulse-triggered
• Edge-triggered

Latch

A Latch is Pulse triggered memory device that checks all its inputs continuously and change its output according to input at any period of time. They do not require Clack for performing the operation.

Example of Latch

S-R Latch

Fig: 1 S-R Latch

The S-R latch can be constructed by using either two NAND or two NOR Gates. When two cross coupled NOR Gates as shown in the figure 1 used then the resultant is the S-R Latch.

Operation:

• It has two Complementary outputs Q and Q’as shown in the figure.
• CASE-I: When Q Output is HIGH, the latch is in SET state.
• CASE-II: When Q Output is LOW, the latch is in RESET state.

S-R Latch Truth Table

Condition for NAND GATE latch

• When R’=LOW and S’=HIGH then Latch is in RESET state.
• When S’=LOW and R’=HIGH then Latch is in SET state.
• When both the inputs are HIGH then Latch is in no change.
• When both the inputs are LOW i.e; Q and Q’ both HIGH this is invalid state.

Draw backs of Latch:
Latch circuits are not preferred suitable for the synchronous logic circuits.

Flip Flops:

Flip Flop is a bistable multivariate which has only two stable states. Simply, Flip Flop samples its input and change its outputs only at the time when it determine that clock signal is activated. They are abbreviated as FF, a  Edge-triggered memory element. They involves two types of triggering procedure

• Positive Edge-triggering when (ON = from 0 to 1; OFF = other time)
• Negative Edge-triggering when (ON = from 1 to 0; OFF = other time)

Types of Flip Flop

Example of Flip Flop

S-R Flip Flop

Fig:2 S-R Flip Flop

It is not desirable to allow a latch to change state at random times. In synchronous operation one pair of gates are connected as an RS flip flop. A second pair, called the steering gate which can be enable by the use of clock signal. This clock allow one or the other gates to pass a SET or RESET signal to the required flip flop.

Operation:

• It has two Complementary outputs Q and Q’as shown in the figure.

Condition for Clocked S-R  Flip Flop

Truth Table of S-R Flip Flop

S-R Flip flop work during the edge triggering of the clock pulse,

• When S=HIGH and R=LOW then Flip Flop is in a SET State.
• When R=HIGH and S=LOW then Flip Flop is in RESET State.
• When both the inputs are LOW then there is a no change State.
• When both the inputs are High i.e; Q and Q’ both Low this is invalid State.