questions and answers on digital electronics Digital electronics is that branch of science which represents signals by dicrete band of analog level. Digital electronics is also that branch of science that uses fibre optics to detect digital display. Most of the reputed electronics companies put up their questions from this portion of electronics. So to assist the aspirants, we are providing here some frequently asked interview questions and answers on digital electronics
Ques 1. Explain about setup time and hold time, what will happen if there is setup time and hold tine violation, how to overcome this?
Ans. For Synchronous flip-flops, we have special requirements for the inputs with respect to clock signal input there are Setup Time: Minimum time Period during which data must be stable before the clock makes a valid transition. E.g. for a positive edge triggered flip-flop having a setup time of 2ns so input data should be Stable for 2ns before the clock makes a valid transaction from zero to one.
Hold Time: Minimum time period during which data must be stable after the clock has made a valid transition. E.g. for a posedge triggered flip-flop, with a hold time of 1 ns. Input Data (i.e. R and S in the case of RS flip-flop) should be stable for at least 1 ns after clock has made transition from 0 to 1 Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge. Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either ‘1’ or ‘0’. This whole process is known as metastability
Please remember that for GATE 2018 exams now you need to start you Prep and start taking online test. We try to guide students through whats app at 9958444212 or email@example.com. We have started online Live coaching for GATE preparations. You can prepare from your home through live coaching classes for GATE/IES/ UPSC
Ques 2. What is difference between latch and flip-flop?
Ans. The main difference between latch and FF is that latches are level sensitive while FF is edge sensitive. They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. FF on the other hand, will store the input only
when there is a rising/falling edge of the clock. Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches. Latches take fewer gates (also less power) to implement than flip-flops. Latches are faster than flip-flops.
Ques 3 Given only two xor gates one must function as buffer and another as inverter?
Ans Tie one of xor gates input to 1 it will act as inverter. Tie one of xor gates input to 0 it will act as buffer.
Ques 4 Difference between Mealy and Moore state machine?
Ans Mealy and Moore models are the basic models of state machines. A state machine which uses only Entry Actions, so that its output depends on the state, is called a Moore model. A state machine which uses only Input Actions, so that the output depends on the state and also on inputs, is called a Mealy model. The models selected will influence a design but there are no general indications as to which model is better. Choice of a model depends on the application, execution means (for instance, hardware systems are usually best realized as Moore models) and personal preferences of a designer or programmer. Mealy machine has outputs that depend on the state and input (thus, the FSM has the output written on edges) Moore machine has outputs that depend on state only (thus, the FSM has the output written in the state itself.
Advantages and Disadvantages
In Mealy as the output variable is a function both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the input signal level. All of the concepts can be applied to Moore-model state machines because any Moore state machine can be implemented as
a Mealy state machine, although the converse is not true. Moore machine: the outputs are properties of states themselves… which means that you get the output after the machine
reaches a particular state, or to get some output your machine has to be taken to a state which provides you the output. The outputs are held until you go to some other state Mealy machine:
Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle.
Ques 5 Difference between one hot and binary encoding?
Ans. Common classifications used to describe the state encoding of an FSM are Binary (or highly encoded) and One hot.A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM.A one hot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop
representing the current or “hot” state) is set at a time in a one hot FSM design. For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a one hot FSM requires a flip-flop for each state in the design FPGA vendors frequently recommend using a one hot state encoding style because flip-flops are plentiful in an FPGA and the combinational logic required to implement a one hot FSM design is typically smaller than most binary encoding styles.
Since FPGA performance is typically related to the combinational logic size of the FPGA design, one hot FSMs typically run faster than a binary encoded FSM with larger combinational logic blocks
Ques 6 How to achieve 180 degree exact phase shift?
a) DCM an inbuilt resource in most of FPGA can be configured to get 180 degree phase shift.
b) BUFGDS that is differential signaling buffers which are also inbuilt resource of most of FPGA can be used. Digital Electronics Solved Questions
Ques 7 What is significance of RAS and CAS in SDRAM?
Ans. SDRAM receives its address command in two address words. It uses a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the row address strobe (RAS). Following the RAS command is the column address strobe (CAS) for latching the second address word. Shortly after the RAS and CAS strobes, the stored data is valid for reading.
Ques 8 Tell some of applications of buffer?
Ans. a) They are used to introduce small delays.
b) They are used to eliminate cross talk caused due to inter electrode capacitance due to close routing.
c) They are used to support high fan-out, e.g.: bufg
9) Give two ways of converting a two input NAND gate to an inverter?
a) Short the 2 inputs of the NAND gate and apply the single input to it.
b) Connect the output to one of the input and the other to the input signal.
Ques 10. Why is most interrupts active low?
Ans. This answers why most signals are active low if you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition respectively. When it goes from high to low it depends on the
pull down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging. Hence people prefer using active low signals.
We hope that the given set of questions and answers on digital electronics satisfies your needs and so we would like to have some feedback from your part so as to improve it. Please put your valuable feedback in the comment the box.
Although we have tried to bring GATE Syllabus of Computer Science and Information Technology 2016 through oureducation research and this research is conducted in Oct 2017 but by the time you decide to take decision in GATE Syllabus of Computer Science and Information Technology 2018, teachers and management of coaching may change so for updated information please mail with contact number ( your number is safe with us) at our email id firstname.lastname@example.org.
Please write your views and comments in the comment box below for quick and better response.Please go through the link and fill this form click here
- Virtual LANs and Network Layer
- Signal degradation in optical fibre
- Frequency Division Multiple Access