# Sample Paper of Digital Electronics

May 18 • Engineering Sample Papers • 2588 Views • 2 Comments on Sample Paper of Digital Electronics

Sample Paper of Digital Electronics covers the questions and answers from Digital Electronic before going to Sample Paper of Digital Electronics we will give introduction of Digital Electronic.

Introduction of Digital Electronic:

The term digital means perform the operations on digits (0,1) or using these digits for producing information in a form that humans can understand.In this section we have describe the Digital Electronic Gates like AND,OR,NOT,NAND,NOR etc.Digital techniques are useful because it is easier to get an electronic device to switch into one of a number of known states than to accurately reproduce a continuous range of values.

## Sample Paper of Digital Electronics

Sample Paper of Digital Electronics cover all the concepts and definition read this section carefully.

Q1.(a) Explain error correcting codes in detail.

Ans. Error correcting codes:

Hamming Code- It is used for error correction. It is a methodical way to add one or more parity bits to a data character in order to detect and correct errors. The Hamming Distance between two codes is defined as the number of bits changed from one code to another.

Q1.(b) Construct hamming code for 10111001 using odd parity.

Ans. There are 8 bits of data, so 4 parity bits are needed.

A 12 bit code with bit positions will be:-

12  11  10  9   8     7    6   5  4    3   2    1   <– Bit Position

1    0    1   1   P8   1    0   0   P4  1  P2   P1  <– Bit

–> Position 1. Checks 1,3,5,7,9,11, it must be 0 to have odd parity.

–> Position 2. Checks 2,3,6,7,10,11, it must be 0 to have odd parity.

–> Position 4. Checks 4,5,6,7,12, it must be 1 to have odd parity.

–> Position 8. Checks 8,9,10,11,12, it must be 0 to have odd parity

So final code word is 101101001100.

Q2. What are the steps of finding minimal SOP?

Ans Step 1: Represent min terms in their binary representations.

Step 2: Arrange all the min terms in increasing order according to the number of 1’s in them.

Step 3: Compare set 1 with set 2, set 2 with set 3, set 3 with set 4 and so on. Find the min terms which differ only by one variable to get 2 cell combinations.

Step 4. Now from the 2 cell combinations, one variable and a dash in the same position can be combined to form the 4 cell combination.

Q3. Explain BCD seven segment decoder.

Ans This type of decoder accepts the BCD code on its input and provides output to energize seven-segment display devices in order to produce a decimal readout.

Lead Displays- One common type of seven segment display consists of light emitting diodes (LEDs). Each segment is an LED that emits light when current flows through it. When a LOW level is applied to a segment input, the LED is forward biased and current flows through it. When a HIGH is applied to a segment input, the LED is forwarded biased and current flows through it.

Q4.(a) Explain the edge triggered JK flip flop.

Ans. The J-K flip flop is very versatile and is perhaps the most widely used type of flip flop. The functioning of the J-K flip flop is identical to that of the S-R flip flop in SET, RESET and no change conditions of operation. The difference is that the J-K flip flop has no invalid state as does the S-R flip flop. Therefore, the J-K flip flop is a very versatile device that finds wide application in digital systems.

`Q4.(b) Explain asynchronous inputs.

Ans. Sometimes we require some fixed output before applying clock pulse. The output may be either low or high. These type of input is taken by applying asynchronous input to the flip flop. These input affect the output of the flip flop and independent to the clock input. There are two such type of input and they are:

1. Preset Input

2. Clear Input

Q5.(a) Describe the operation of basic ECL circuit.

Ans. Emitter Coupled Logic (ECL) circuit like TTL is a bipolar technology and consists of a differential amplifier, a bias circuit for stabilization of transistor and emitter follower outputs. ECL is much faster than TTL because the transistors do not operate in saturation and is used in more specialized high speed operation.

Emitter follower circuit is used for impedance matching. Because of the low output impedance of the emitter follower and the high input impedance of the differential amplifier input, high fan out operation is possible. In this type of circuit saturation is not possible.

Q5.(b) Explain the operation of a CMOS NOR gate.

Ans. The operation of a CMOS NOR gate is explained below:

1. When inputs A and B are low, Q1 and Q2 are ON, Q3 AND Q4 are OFF. Therefore output is pulled High through Q1 and Q2 in series to +VDD.

2. When both inputs A and B are HIGH Q1 and Q2 are OFF, and Q3 and Q4 are ON. Therefore the output is pulled LOW through Q3 and Q4 in parallel to ground.

3. When input A is LOW and input B is HIGH, Q1 and Q4 are ON, Q2 and Q3 are OFF, therefore the output is pulled LOW through Q4 to ground.

4. When input A is high and input B is low, Q2 and Q3 are ON, Q1 and Q4 are OFF, therefore the output is pulled LOW through Q3 to ground.

Q6.(a) Compare PMOS with NMOS.

Ans. 1. PMOS (p-channel MOSFET) is much easier to produce than tne n-channel device (NMOS).

2. NMOS is about twice as fast as PMOS due to smaller junction areas.

3. PMOS device must have more than twice the area of the n-channel to achieve the same resistance.

4. NMOS fabrication devices need much extensive control and are much expensive than PMOS devices.

5. PMOS device has more than the twice the ON resistance of an equivalent NMOS of the same geometry.

Q6.(b) Explain CMOS characteristics in detail.

Ans. Some of the important CMOS characteristics are as follows:

1. Power Supply Voltage

2. Logic Voltage Levels

3. Noise Margins

4. Power Dissipation

5. Fan Out

6. Switching Speed

7. Unused Inputs

8. Static Sensitivity

Q7.(a) Explain architecture of ROM using OR gates and diodes.

Ans. 32 x 4 ROM using OR gates- ROM is a combinational circuit with AND gates connected as decoder, and the number of OR gates is equal to the number of output lines in the unit. The internal logic constructions of a 32 x 4 ROM: The five input variables are decoded into 32 lines by means of 32 AND gates and 5 inverters. Each one of the 32 addresses selects one and only one output of the decoder.

Q7.(b) Write short notes on :

1.PAL                                2.FPGA

Ans. 1. PAL- programmable array logic is a type of fixed architecture logic device with programmable AND gates followed by fixed OR gates. Because of the reason that only AND gates are programmable. whereas OR gates are fixed, PAL is not as flexible as PLA. The PAL has same AND and OR arrays.

2. FPGA- Field programmable gate array is a flexible architecture programmable logic device. It is a single VLSI (very large scale integrated chip) circuit constructed on a single piece of silicon. It consists of identical individually programmable rectangular modules.

Q8.(a) List some specification of D/A converter.

Ans. Some important specifications are:

1. Accuracy

2. Offset Voltage

3. Monotonicity

4. Settling Time

5. Linearity

6. Resolution (Step Size)

7. Temperature Sensitivity

Q8.(b) Explain counter type A/D converter.

Ans. The counter type A/D converter is constructed using only one comparator with a variable reference voltage. The variable reference voltage can be obtained using a sequence counter and a D/A converter.

1. Counter type ADC is very simple and needs less hardware compared to the simultaneous A/D converter.

2. It is a better method for digitizing with high resolution.

Conversion time is very long, variable and proportional to the amplitude of the analog input voltage.

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